View SC2440TETRT_4114118.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

2.5 MHz Dual Switching Regulator with Integrated 2A Switches
POWER MANAGEMENT Description
The SC2440 is an adjustable frequency dual currentmode switching regulator with 2A integrated switches. Its high frequency operation allows the use of small inductors and capacitors, resulting in very compact power supplies. The SC2440 is suitable for next generation XDSL modems requiring operating frequencies in excess of 1.5 MHz. The two channels operate at 180 out of phase for reduced input voltage ripples. Separate soft start/ shutdown pins allow independent control and output sequencing for latch-up prevention. The SC2440 can also be externally synchronized up to 2.5 MHz per channel. Current-mode PWM control allows fast transient response with simple loop compensation. Cycle-by-cycle current limiting and hiccup overload protection reduce power dissipation during overload.
SC2440
Features
u Up to 2.5 MHz/Channel Programmable Switching u u u u u u u u u u u u u u u u u
Frequency Fixed Frequency Current-mode Control Wide Input Voltage Range 2.8V to 20V Out of Phase Switching Reduces Ripple Cycle-by-cycle Current-limiting Independent Shutdown/soft-start Pins Independent Hiccup Overload Protection Independent Power-Good Indicators Two 2A Integrated Switches External Synchronization Thermal Shutdown Thermally Enhanced 16-pin TSSOP Package XDSL and Cable Modems Set-up Boxes Point of Load Applications CPE Equipment DSP Power Supplies Disk Drives
Applications
Typical Application Circuit
R6 100K FB1 PGOOD1 BOOST1 D3 C2 1N4148 0.1F L1 COMP1 C7 10pF SS1 22nF R9 ROSC C10 22nF C9 COMP2 R7 10pF C8 24.3K 220pF FB2 GND BOOST2 R8 PGOOD2 100K 1N4148 SW2 C4 0.1F 15K SS2 SYNC SW1 VIN 12V C15 IN 10F D2 UPS120 L2 4.4H D4 C3 10F R4 10K R3 40.2K OUT2 5V/2A 3.3H D1 UPS120 C1 10F R1 23.3K R2 10K
R5
C5
Efficiency vs Load Current
95
OUT1 3.3V/2A
15.4K C6 470pF
90 85 Efficiency (%) 80 75 70 65 60 55 50 0
VIN = 12V
VOUT2 = 5V
SC2440
V OUT1 = 3.3V
0.5
1
1.5
2
L1: Sumida CR43 L2: F alco D04012
Load Current (A)
Figure 1. 1.3MHz 12V to 3.3V and 5V Step-down Converter
Revision: March 5, 2007 1 www.semtech.com
SC2440
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Input Voltage Boost Pin Boost Pin Above SW PGOOD Pin Voltage SS Pins FB Pins SYNC Pin Current SW Voltage SW Transient Spikes (<10ns Duration) Operating Ambient Temperature Range Thermal Resistance Junction to Ambient Maximum Junction Temperature Storage Temperature Range Lead Temperature (Soldering)10 sec
Symbol VIN VBST VBST-VSW VPGOOD VSS VFB ISYNC VSW VSW TA JA TJ TSTG TLEAD
Max -0.3 to 20 40 20 VIN 3 -0.3 to VIN 5 -0.6 to VIN VIN +1.5 -2.5 -40 to 85 45 150 -65 to +150 300
Units V V V V V V mA V V C C/W C C C
Electrical Characteristics
Unless specified: -40C < TA < 85C, -40C < TJ< 105C, ROSC = 12.1K, VSYNC = 0, V IN = 5V, VBOOST = 8V
Parameter V IN Start Voltage V IN Start Hysteresis Quiescent Current Shutdown Current Feedback Voltage Feedback Voltage Line Regulation FB Pin Input Bias Current Error Amplifier Transconductance Error Amplifier Open-loop Gain COMP Source Current COMP Sink Current COMP Pin to Switch Current Gain
(c) 2005 Semtech Corp.
Conditions
Min 2.45
Typ 2.62 75
Max 2.78
Units V mV
Not switching, PGOOD Open V SS1 = VSS2 = 0V, PGOOD Open 0.980 V IN = 3V to 20V V FB = 1V, V COMP = 1.5V
3.3 38 1.000 0.005 -15 280 53
4.3 60 1.020
mA A V %/V
-30
nA -1 dB A A A/V
V FB = 0.8V, V COMP = 1.5V V FB = 1.2V, V COMP = 1.5V
2
20 20 5.7
www.semtech.com
SC2440
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: -40C < TA < 85C, -40C < TJ< 105C, ROSC = 12.1K, VSYNC = 0, V IN = 5V, VBOOST = 8V
Parameter COMP Switching Threshold COMP Maximum Voltage Channel Switching Frequecy Maximum Duty Cycle Switch Current Limit Switch Saturation Voltage Switch Leakage Current Minimum Boost Voltage Boost Pin Current
Conditions
Min 0.7
Typ 1.1 2.2
Max 1.3
Units V V
VFB = 0.9V 1.2 (Note 2) V FB = 0.9V, VSS = 2.3V, COMP Pin Open ISW = -2A 80 2
1.4 90 2.6 0.3
1.6
MHz % A
0.48 10
V A V mA mA V A A A V V
ISW = -2A ISW = -0.5A ISW = -2A
1.8 20 60 0.2 0.4 2 1.8 0.8 2 0.74 0.7 80 1 100 0.2 0.1 2
2.5 30 80 0.7
Minimum Soft-Start Voltage to Exit Shutdown Soft-start Charging Current
SS1 Tied to SS2 VSS = 0V VSS = 1.5V
Soft-start Discharging Current Minimum Soft-start Voltage to Enable Overload Shutoff FB Overload Threshold Soft-start Voltage to Restart Switching After Overload Shutoff Power Good Threshold Below FB Power Good Output Low Voltage Power Good Pin Leakage Current SYNC Input High Voltage SYNC Input Low Voltage SYNC Frequency SYNC Pin Input Current Thermal Shutdown Temperature Thermal Shutdown Hysteresis
VSS = 1.5V V SS Rising V SS = 2.3V, VFB Falling VSS Falling VFB Rising VFB = 0.8V, IPGOOD = 250A VPGOOD = 5V
1.3 120 0.4 1
V mV V A V
(Note 1) SYNC Frequency = 2 X Channel Frequency. (Note 1) VSYNC = 2V 3.4 60 155 10
0.8 5 75
V MHz A C C
Notes: (1) Guaranteed by design, not tested in production. (2) The maximum duty cycle specified corresponds to 1.4MHz switching frequency. Duty cycles higher than those specified can be achieved by lowering the operating frequency. (3) This device is ESD sensitive. Use of standard ESD handling precautions is required.
(c) 2005 Semtech Corp.
3
www.semtech.com
SC2440
POWER MANAGEMENT Pin Configuration
TOP VIEW
BOOST1 SW1 IN SYNC ROSC IN SW2 BOOST2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FB1 COMP1 PGOOD1 SS1 SS2 PGOOD2 COMP2 FB2
Ordering Information
Part Number SC2440TETRT SC2440EVB Package(1)(2) TSSOP-16 EDP Evaluation Board
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant.
(16 Pin TSSOP-EDP)
Underside metal must be soldered to ground.
Pin Descriptions
Pin # 1, 8 2, 7 3, 6 Pin Name BOOST1, BOOST2 SW1, SW2 IN Pin Function Supply pins to the power transistor drivers.Tie to external diode-capacitor charge pumps to generate drive voltages higher than VIN in order to fully saturate the internal NPN power switches. Emitters of the internal power NPN transistors. Connect to the inductors, the freewheeling diodes and the boost capacitors. Input power supply pins of the SC2440 and also the common collector of the internal power NPNs. Pins 3 and 6 are internally tied together and must be locally bypassed. Driving the SYNC pin with an external clock synchronizes both step-down converters. The external clock frequency must be at least twice the individual regulator set (or free-running) frequency. Tie this pin to ground if not used. An external resistor between this pin and the ground sets the master oscillator free-running frequency. The set frequency is twice that of the individual switching regulator. The inverting inputs of the error amplifiers. Each FB pin is tied to a resistive divider between its output and the ground for setting the channel output voltage. These are the outputs of the internal error amplifiers. The voltages on these pins control the peak switch currents. RC networks at these pins compensate the control loops. Pulling either pin below 0.7V stops the corresponding switching regulator. Open collector outputs of the Power Good comparators. Tie to external pull-up resistors from the input or the output of the converter. The PGOOD outputs become valid as soon as VIN rises above 1 V BE during power-up. PGOOD is actively pulled low until the corresponding FB pin rises to within 10% of the final regulation voltage. A capacitor from either SS pin to the ground provides soft-start and overload hiccup functions for that channel. Pulling either SS pin below 0.8V with an open drain or collector transistor shuts off the corresponding regulator. To completely shut off the SC2440 to low-current state, pull both SS pins to the ground. Soft-start is recommended for all applications. The exposed pad at the bottom of the package is the electrical ground connection of the SC2440. It also provides a thermal contact to the circuit board. It is to be soldered to the ground plane of the board.
4 www.semtech.com
4
SYNC
5 9, 16
ROSC FB1, FB2 COMP1, COMP2
10, 15
11, 14
PGOOD1, PGOOD2
12, 13
SS1, SS2
Underside Metal
(c) 2005 Semtech Corp.
GND
SC2440
POWER MANAGEMENT Block Diagrams
3 IN
PGOOD1
14
+ POWER GOOD 100mV
+ +
+ ISEN 7.7m + ILIM 20mV
SLOPE COMP 1
COMP1
15
BOOST1
1
FB1
16
EA +
+ PWM -
S Q R POWER TRANSISTOR
SS1
13
FB1
2 SW1
1V SS2
12
0.74V FAULT
REFERENCE & THERMAL SHUTDOWN SLOPE COMP 1
Soft-Start And Overload Hiccup Control 1
OVLD
SLOPE COMP 2
ROSC
5
SLOPE COMP OSCILLATOR CLK1 FREQUENCY CLK2 DIVIDER
SYNC
4
Figure 2. SC2440 Functional Diagram (One of Two Converters Shown)
FB 0.74V SS + 1.8A R 1V/2 V
S Q OVLD
FAULT 2.6A
Figure 3. Details of the Soft-Start and Overload Hiccup Control Circuit
(c) 2005 Semtech Corp. 5 www.semtech.com
SC2440
POWER MANAGEMENT Typical Characteristics
Feedback Voltage vs Temperature
1.02 V IN = 5V 1.01 1000
Frequency Setting Resistor vs Channel Frequency
Channel Frequency vs Temperature
1.6 ROSC =12.1K
VFB (V)
1.00
ROSC (K )
100
Frequency (MHz)
3
V IN = 5V
1.5
1.4
0.99
10 0.98
1.3
0.97 -50 -25 0 25 50 75 100 125 Temperature (C)
1 0 0.5 1 1.5 2 2.5 Frequency (MHz)
1.2 -50 -25 0 25 50 75 100 125 Temperature (C)
VIN Start Threshold vs Temperature
2.8
400
Switch Saturation Voltage vs Switch Current
80
125C
Boost Pin Current vs Switch Current
V IN = 5V
VIN Threshold (V)
2.7
VCESAT (mV) 300 -40C
Boost Pin Current (mA)
V BST = 8V
60
-40C
2.6
40
125C
200
2.5
25C
20
2.4 -50 -25 0 25 50 75 100 125 Temperature (C)
100 0.0 0.5 1.0 1.5 2.0 2.5 Switch Current (A)
0
0.0 0.5 1.0 1.5 2.0 2.5 Switch Current (A)
Switch Current Limit vs Temperature
3.0 1.8
SYNC Input Logic Thresholds vs Temperature
0.40
SS Shutdown Threshold vs Temperature
VSS1 = VSS2
SYNC Thresholds (V)
2.8 Current Limit (A)
2.6
V IH 1.4 V IL 1.2
SS Threshold (V)
75 100 125
1.6
0.35
0.30
2.4
2.2
0.25
2.0 -50 -25 0 25 50 75 100 125 Temperature (C)
1.0 -50 -25 0 25 50 Temperature (C)
0.20 -50 -25 0 25 50 75 100 125 Temperature (C)
(c) 2005 Semtech Corp.
6
www.semtech.com
SC2440
POWER MANAGEMENT Typical Characteristics
VIN Shutdown Current vs VIN
150 125
VIN Current ( A)
V IN Current (mA) 4 25C -20
VIN Quiescent Current vs VIN
0
Soft-Start Pin Current vs Soft-Start Voltage
T = 25C V IN =5V
100 75
105C
3 105C 2 -40C I SS ( A) -40 -60 -80 1 -100
ISS of the Swept Channel
-40C
50 25
SS1 = SS2 = 0
ISS of the Other Channel (V SS = 0)
0
0 5 10 VIN (V) 15 20
0 0 5 10 V IN (V) 15 20
-120 0.0 0.5 1.0 V SS (V) 1.5 2.0
VIN Supply Current vs Soft-Start Voltage
4 TA = 25C 3
FB Overload Threshold vs Temperature
1.0
PGOOD Threshold to Feedback Difference Voltage vs Temperature
-90
0.9 FB Threshold (V)
-92 Voltage (mV)
-50 -25 0 25 50 75 100 125
IIN (mA)
0.8
-94
2 VIN = 5V 1 VSS1 = V SS2 VCOMP1 = 0 VCOMP2 = 0 0 0.0 0.5 1.0 VSS (V) 1.5 2.0
0.7
-96
0.6
-98
0.5 Temperature (C)
-100 -50 -25 0 25 50 75 100 125 Temperature (C)
(c) 2005 Semtech Corp.
7
www.semtech.com
SC2440
POWER MANAGEMENT Operation
The SC2440 is a 2-channel constant-frequency peak current-mode step-down switching regulator with integrated 2A power transistors. Both regulators of the SC2440 operate from a common input power supply and share the same voltage reference, the master oscillator and the synchronizing circuit. Turn-on of the power transistors are phase-shifted by 180. The two regulators are otherwise completely identical, independent and are capable of producing two separate outputs from the same input. The master oscillator of the SC2440 runs at twice the channel frequency. The free-running frequency of the master oscillator can be programmed with an external resistor from the ROSC pin to ground. Frequency adjustability makes switching regulator design flexible. Peak current-mode control is utilized for the SC2440. The double reactive poles of the output LC filter are reduced to a single real pole by the inner current loop, easing loop compensation. Fast transient response can be achieved with a simple Type-2 compensation network. Switch collector current is sensed with an integrated 7.7m sense resistor. The sensed current is summed with slopecompensating ramp before it is compared with the transconductance error amplifier output. The PWM comparator tripping instant determines the switch turnon pulse width (Figure 2). The current-limit comparator ILIM turns off the power switch when the sensed-signal exceeds the 20mV current-limit threshold. ILIM therefore provides cycle-by-cycle limit. Current-limit does not vary with duty-cycle. Driving the base of the power transistor above the input power supply rail minimizes the power transistor turn-on voltage and maximizes efficiency. An external charge pump (formed by the capacitor C2 and the diode D3 in Figure 1) generates a voltage higher than the input rail at the BOOST pin. The bootstrapped voltage generated becomes the supply voltage for the power transistor driver. The SS pin is a multiple-function pin. An external capacitor connected from the SS pin to the ground together with the internal 1.8A and 2.6A current sources set the soft-start and overload shutoff times of the regulator (Figure 3). The SS pin can also be used to shut off the corresponding regulator. When either SS pin is pulled below 0.8V, that regulator is turned off. If both SS pins are pulled below 0.2V, then the SC2440 undergoes overall shutdown. The current draw from the input power supply reduces to 38A. When either SS pin is released, the corresponding softstart capacitor is charged with a 2A current source (not shown in Figure 3). As either SS voltage exceeds 0.3V, the internal bias circuit of the SC2440 is enabled. The SC2440 draws 3.3mA from VIN. An internal fast charge circuit quickly charges the soft-start capacitor to 1V. At this juncture, the fast charge circuit turns off and the 1.8A current source slowly charges the soft-start capacitor. The output of the error amplifier is forced to track the slow soft-start ramp at the SS pin. When the COMP voltage exceeds 1.1V, the switching regulator starts to switch. During soft-start, the current limit of the converter is gradually increased until the converter output comes into regulation. Hiccup overload protection is utilized in the SC2440. Overload shutdown is disabled during soft-start (VSS < 2V). In Figure 3 the reset input of the overload latch will remain high if the SS voltage is below 2V. Once the softstart capacitor is charged above 2V, the overload shutdown latch is enabled. As the load draws more current from the regulator, the current-limit comparator will limit the peak inductor current. This is cycle-by-cycle current limiting. Further increase in load current will cause the output voltage to decrease. If the output voltage falls below 74% of its set point, then the overload latch will be set and the soft-start capacitor will be discharged with a net current of 0.8A. The switching regulator is shut off until the soft-start capacitor is discharged below 1V. At this moment, the overload latch is reset. The soft-start capacitor is recharged and the converter again undergoes soft-start. The regulator will go through soft-start, overload shutdown and restart until it is no longer overloaded. Each regulator of the SC2440 has its own power good comparator. The open collector output of the power good comparator will be actively pulled low if the corresponding feedback voltage is below 0.9V.
(c) 2005 Semtech Corp.
8
www.semtech.com
SC2440
POWER MANAGEMENT Applications Information
Setting the Output Voltage The regulator output voltage is set with an external resistive divider (Figure 4) with its center tap tied to the FB pin.
VOUT
Choosing the Operating Frequency The free-running frequency of the master oscillator is set with an external resistor from the ROSC pin to ground. Channel frequency is one-half of that of the master oscillator. A graph of channel frequency against ROSC is shown in the "Typical Performance Characteristics". Before choosing the operating frequency, tradeoffs among efficiency, operating duty cycle, component size and EMI interferences must be considered. High frequency operation reduces the size of passive components but switching losses are higher. Lowering the switching frequency improves efficiency. However the required inductor and capacitor are larger. Channel frequencies between 1 and 2MHz are good compromises. In order to quantify the tradeoff between switching frequency and efficiency, the 12V to 5V DC-DC converter in Figure 1 is modified to run at 500KHz and 2.5MHz while keeping the inductor ripple current constant. The modified component values are tabulated in Table 1 and efficiencies at these frequencies are shown in Figure 5. The efficiency of the 1.3MHz 5V regulator in Figure 1 is also plotted for the ease of comparison. The efficiency at 500KHz is only marginally higher than that at 1.3MHz. The peak efficiency at 2.5MHz is only 2% lower compared to those at lower frequencies.
R1 15nA
FB
SC2440
R2
Figure 4. VOUT is set with a Resistive Divider
R1 = R2 (VOUT - 1)
(1)
The percentage error due the input bias current of the error amplifier is
R VOUT - 15nA 100 (R1 2 ) = . VOUT 1V
Example: Determine the output voltage error of a VOUT = 5 V converter with R2 = 51.1K . From (1),
R1 = 51.1K (5 - 1) = 205K
VOUT - 15nA 100 (51.1K205K) = = -0.061% . VOUT 1V
This error is at least an order of magnitude lower than the ratio tolerance resulting from the use of 1% resistors in the divider string.
Efficiency vs Load Current
90
500KHz
Efficiency (%)
85
1.3MHz 2.5MHz
80
VIN=12V VOUT =5V
f (MHz) 0.5 1.3 2.5
R9 (K) 53.6 15.0 4 .0 2
L2 (H) 10 (Coiltronics DR73-100) 4.44 (Falco D04012) 2.7 (Sumida CR43-2R7)
R7 (K) 12.4 24.3 32.4
C8 (pF) 470 220 220
C9 (pF) 22 10 10
75 0.0 0.5 1.0 1.5 2.0
Load Current (A)
Table 1. The 12V to 5V Converter in Figure 1 is modified to run at Different Frequencies.
(c) 2005 Semtech Corp. 9
Figure 5. Efficiencies of 500KHz, 1.3MHz and 2.5MHz 12V to 5V Step-down Converters.
www.semtech.com
SC2440
POWER MANAGEMENT Applications Information
Minimum On Time Consideration The operating duty cycle of a step-down switching regulator with diode rectifier in continuous-conduction mode (CCM) is given by D2 = 3.3 + 0.45 = 0.28 13.2 + 0.45 - 0.25
Minimum On Time vs Temperature
130
TON(MIN) (ns)
VOUT + VD D= VIN + VD - VCESAT
120
(2)
110
where VCESAT is the switch saturation voltage and VD is voltage drop across the rectifying diode.
100
VIN ratio. In peak Duty cycle decreases with increasing VOUT
current-mode control, the PWM modulating ramp is the sensed current ramp of the power switch. This current ramp is absent unless the switch is turned on. The intersection of this ramp with the output of the voltage feedback error amplifier determines the switch pulse width. The propagation delay time required to immediately turn off the switch after it is turned on is the minimum switch on time (T ON (MIN) ). Closed-loop measurement of the SC2440 with low
90
80 -40 -20 0 20 40 60 80 100 Temperature (C)
Figure 6. Variation of Minimum On Time with Temperature. If the ambient temperature can be as high as 85C, then the maximum operating frequencies of the 1.0V and the 3.3V converters will be D2 . = 2.3MHz respectively. 120ns Channel frequency should be set below 920KHz to allow margin for load transient. Minimum Off Time Limitation The PWM latch in Figure 2 is reset every period by the clock. The clock also turns off the power transistor to refresh the bootstrap capacitor. This minimum off time limits the attainable duty cycle of the regulator at a given switching frequency. Measurement shows that the power transistor needs to be turned off for at least 120ns every switching period to properly reset the latch and to refresh the bootstrap capacitor. For a step-down converter, D increases with increasing D1 = 920KHz 120ns and
VOUT ratios shows VIN
that the minimum on time is about 105ns at room temperature. T ON (MIN) also exhibits a slight positive temperature coefficient (Figure 6). The power switch in the SC2440 is either not turned on at all or for at least D TON(MIN). If the required switch on time (= ) is shorter f than the minimum on time, the regulator will either skip cycles or it will jitter. Example: Determine the maximum operating frequency of a dual 12V to 1.0V and 12V to 3.3V switching regulator using the SC2440. Assuming that VD = 0.45V, VCESAT = 0.25V and VIN = 13.2V (10% high line), the corresponding duty ratios, D1 and D2, of the 1.0V and 3.3V converters can be calculated using (2). 1 + 0.45 D1 = = 0.11 13.2 + 0.45 - 0.25
VOUT ratio. If the required duty VIN
cycle is higher than the attainable maximum, then the
10 www.semtech.com
(c) 2005 Semtech Corp.
SC2440
POWER MANAGEMENT Applications Information
output voltage will not be able to reach its set value in continuous-conduction mode. Example: Determine the maximum operating frequency of a dual 3.3V to 1.8V and 3.3V to 2.5V switching regulator using the SC2440. Assuming that VD = 0.45V, VCESAT = 0.25V and VIN = 2.97V (10% low line), the duty ratios D1 and D 2 of the 1.8V and 2.5V converters can be calculated using (2). D1 = 1.8 + 0.45 = 0.71 2.97 + 0.45 - 0.25 2.5 + 0.45 = 0.93 . 2.97 + 0.45 - 0.25 the set frequency of master oscillator because the amplitudes of the internal sawtooth ramp and slope compensation ramp will both be significantly reduced. Example: Choose the value of R OSC to externally synchronize the SC2440 to 2MHz per channel. channel The required synchronizing clock frequency = 2 times the channel frequency = 4MHz. For a given ROSC, the free-running channel frequency has a tolerance of 15%. Set the nominal free-running channel frequency to 2 MHz = 1.73 MHz to ensure locking. 1.15 Looking up the graph "Channel Frequency vs. ROSC" in the Typical Characteristics, ROSC = 9.31K for a set frequency of 1.73MHz. With 15% tolerance, the set channel frequency can vary from 0.85 (1.73 ) = 1.47MHz to 1.15 (1.73 ) = 2MHz . Therefore Synchronizing Frequency 2 = = 1.36 . Lowest Free - running Frequency 1.47 Inductor Selection The inductor ripple current IL for a non-synchronous step-down converter in continuous-conduction mode is
IL = ( VOUT + VD )(1 - D) ( VOUT + VD )( VIN - VOUT - VCESAT ) = fL ( VIN + VD - VCESAT ) fL
D2 =
The maximum operating frequencies of the 1.8V and the 2.5V converters are therefore 1 - D2 . = 580KHz respectively. 120ns Transient headroom requires that channel frequency be lower than 580KHz. External Synchronization The SYNC input buffer is positive-edge triggered and TTLcompatible ( VIL < 0.8 V and VIH > 2V ). The free-running master oscillator generates a periodic sawtooth ramp between two threshold voltages. A faster external clock applied to the SYNC pin discharges the internal ramp before it reaches its upper threshold, thus locking the internal oscillator. As shown in Figure 2, the master oscillator is being synchronized not the individual phases (see Figure 2). The synchronizing frequency should be twice the desired channel frequency. Bench test shows that an external clock with frequency ranging from slightly below twice to at least 3.5 times the channel freerunning frequency is capable of locking the master oscillator. To ensure frequency locking, the external clock frequency should be at least twice the highest freerunning channel frequency. The frequency of the synchronizing clock should not be higher than 1.6 times
(c) 2005 Semtech Corp. 11
1 - D1 = 2.4MHz and 120ns
(3) where f is the switching frequency and L is the inductance. In current-mode control, the slope of the modulating (sensed switch current) ramp should be steep enough to lessen jittery tendency but not so steep that large flux swing decreases efficiency. Inductor ripple current IL between 25-40% of the peak inductor current limit is a good compromise. Inductors so chosen are optimized
www.semtech.com
SC2440
POWER MANAGEMENT Applications Information
in size and DCR. Setting IL = 0.3(2) = 0.6 A , VD = 0.45 V and VCESAT = 0.25 V in (3), ( V + 0.45)( VIn - VOUT - 0.25) L = OUT ( VIN + 0.2)(0.6) f where L is in H and f is in MHz. Equation (3) shows that for a given VOUT , IL increases as D decreases. If VIN varies over a wide range, then choose L based on the nominal input voltage. Always verify converter operation at the input voltage extremes. The peak current limits of both SC2440 power transistors are internally set at 2.6A. The peak current limits are duty-cycle invariant and are guaranteed higher than 2A. The maximum load current is therefore conservatively IOUT (MAX ) = ILM - IL I = 2A - L 2 2 (5) (4)
2 Power dissipated in the input capacitor is IRMS( CIN) (ESR) .
IOUT 1 ( at D = ), 2 2 corresponding to the worst-case power dissipation
Equation (6) has a maximum value of I2 ESR OUT in CIN. 4
A dual-channel step-down converter with interleaved switching reduces the RMS ripple current in the input capacitor to a fraction of that of a single-phase buck converter. If both power transistors in the SC2440 were to switch on in phase, the current drawn by the SC2440 would consist of current pulses with amplitude equal to the sum of the channel output currents. If each channel were delivering IOUT and operating at 50% duty cycle, then the input current would switch from zero to 2IOUT. The RMS ripple current in the input capacitor would then be IOUT. Power dissipated in CIN would be I2 ESR , 4 times OUT that of a single-channel converter. The SC2440 produces the highest RMS ripple current in CIN when only one channel is running and delivering the maximum output current ( 1.5 - 2A ). The input capacitor therefore should have a RMS ripple current rating of at least 1A. Multi-layer ceramic capacitors, which have very low ESR (a few m) and can easily handle high RMS ripple current, are the ideal choice for input filtering. A single 4.7F or 10F X5R ceramic capacitor is adequate. For high voltage applications, a small ceramic (1F or 2.2F) can be placed in parallel with a low ESR electrolytic capacitor to satisfy both the ESR and bulk capacitance requirements. Output Capacitor The output ripple voltage VOUT of a buck converter can be expressed as
1 VOUT = IL ESR + 8 fC OUT
If IL = 0.3 ILM , then IOUT(MAX ) = ILM - IL 0.3ILM = ILM - = 0.85 ILM . 2 2
The saturation current of the inductor should be 20-30% higher than the peak current limit (2A). Low-cost powder iron cores are not suitable for high-frequency switching power supplies due to their high core losses. Inductors with ferrite cores should be used. Input Capacitor A buck converter draws pulse current with peak-to-peak amplitude equal to its output current IOUT from its input supply. An input capacitor placed between the supply and the buck converter filters the AC current and keeps the current drawn from the supply to a DC constant. The input capacitance CIN should be high enough to filter the pulse input current. Its equivalent series resistance (ESR) should be low so that power dissipated in the capacitor does not result in significant temperature rise and degrade reliability. For a single channel buck converter, the RMS ripple current in the input capacitor is IRMS( CIN) = IOUT D(1 - D) .
(c) 2005 Semtech Corp.
(7)
where COUT is the output capacitance. Inductor ripple current IL increases as D decreases (Equation (3)). The output ripple voltage is therefore the highest when VIN is at its maximum. The first term in (7)
12 www.semtech.com
(6)
SC2440
POWER MANAGEMENT Applications Information
results from the ESR of the output capacitor while the second term is due to the charging and discharging of COUT by the inductor ripple current. Substituting IL = 0.6A, f = 1MHz and COUT = 10F ceramic with ESR = 3m in (7),
VOUT = 0.6 A (3m + 12.5m) = 1.8mV + 7.5mV = 9.3mV
Depending on operating frequency and the type of capacitor, ripple voltage resulting from charging and discharging of COUT may be higer than that due to ESR. A 10F or 22F X5R ceramic capacitor is found adequate for output filtering in most applications. Ripple current in the output capacitor is not a concern because the inductor current of a buck converter directly feeds COUT, resulting in very low ripple current. Avoid using Z5U and Y5V ceramic capacitors for output filtering because these types of capacitors have high temperature and high voltage coefficients. Freewheeling Diode Use of Schottky barrier diodes as freewheeling rectifiers reduces diode reverse recovery input current spikes, easing high-side current sensing in the SC2440. These diodes should have a RMS current rating between 1A and 2A and a reverse blocking voltage of at least 5V higher than the input voltage. For switching regulators operating at low duty cycles (i.e. low output voltage to input voltage conversion ratios), it is beneficial to use freewheeling diodes with somewhat higher RMS current ratings (thus lower forward voltages). This is because the diode conduction interval is much longer than that of the transistor. Converter efficiency will be improved if the voltage drop across the diode is lower. The freewheeling diodes should be placed close to the SW pins of the SC2440 to minimize ringing due to trace inductance. Surface-mount equivalents of 1N5817 and 1N5819, MBRM120LT3 (ON Semi), UPS120 and UPS140 (Micro-Semi) are all suitable. Bootstrapping the Power Transistors To maximize efficiency, the turn-on voltage across the internal power NPN transistors should be minimized. If these transistors are to be driven into saturation, then their bases will have to be driven from a power supply
(c) 2005 Semtech Corp. 13
higher in voltage than VIN. The required driver supply voltage (at least 2.5V higher than the SW voltage over the industrial temperature range) is generated with a bootstrap circuit (the diode DBST and the capacitor CBST in Figure 8). The bootstrapped output (the common node between DBST and CBST) is connected to the BOOST pin of the SC2440. The power transistor in the SC2440 is first switched on to build up current in the inductor. When the transistor is switched off, the inductor current pulls the SW node low, allowing CBST to be charged through DBST. When the power switch is again turned on, the SW voltage goes high. This brings the BOOST voltage to VSW + VC BST , thus back-biasing DBST. CBST voltage increases with each subsequent switching cycle, as does the bootstrapped voltage at the BOOST pin. After a number of switching cycles, CBST will be fully charged to a voltage approximately equal to that applied to the anode of DBST. Figure 7 shows the typical minimum BOOST to SW voltage required to fully saturate the power transistor. This differential voltage ( = VC BST ) must be at least 1.8V at room temperature. This is also specified in the "Electrical Characteristics" as "Minimum Bootstrap Voltage". The minimum required V C BST increases as temperature decreases. The bootstrap circuit reaches equilibrium when the base charge drawn from CBST during transistor on time is equal to the charge replenished during the off interval.
Minimum Bootstrap Voltage vs Temperature
2.4
2.2 Voltage (V)
2.0
1.8
1.6
1.4 -50 -25 0 25 50 75 100 Temperature (C)
Figure 7. Typical Minimum Bootstrap Voltage Required to Maintain Saturation at ISW = 2A.
www.semtech.com
SC2440
POWER MANAGEMENT Applications Information
MAX VBST = VIN+ VOUT
DBST DBST
MAX V BST = 2VIN
BOOST VIN IN SW
CBST VOUT VIN IN D
BOOST
CBST VOUT SW
SC2440
GND
SC2440
RECT GND
D
RECT
(a)
(b)
VS > 2.5V
DBST
MAX VBST = VIN + VS
VS > VIN + 2.5V
DBST
MAX V BST = VS
BOOST VIN IN SW
CBST VOUT VIN IN D
BOOST VOUT SW
SC2440
GND
SC2440
RECT GND
D
RECT
(c)
(d)
Figure 8. Methods of Bootstrapping the SC2440. higher than the minimum shown in Figure 7 to maximize efficiency. DBST can be tied either to the input or to the output of the DC/DC converter. If DBST is tied to the input, then the charge drawn from the input power supply will be I SW TON (the base charge of the switch). The energy loss due to base charge per cycle is I SW VIN TON DISW VIN I SW VOUT for a power loss of .
The switch base current =
ISW I SW , where ISW and a+1 a are the switch emitter current and current gain respectively, is drawn from the bootstrap capacitor CBST. Charge I SW TON is drawn from CBST during the switch on a I SW TON . If ISW = 2A, aCBST
time, resulting in a voltage droop of
TON = 1s, = 35 and CBST = 0.1F, then the VCBST droop will be 0.57V. CBST is refreshed to VA - VDBST + VDRECT every y cycle, where VA is the applied DBST anode voltage. Switch base current discharges the bootstrap capacitor to VA - VDBST + VDRECT - ISW TON at the end of conduction. The CBST
If DBST is tied to the output, then the charge drawn from the output capacitor will still be due to base charge per cycle is
14
I SW TON . The energy loss I SW VOUT TON for a power
www.semtech.com
difference between this voltage and that at SW must be
(c) 2005 Semtech Corp.
SC2440
POWER MANAGEMENT Applications Information
loss of DISW VOUT . BOOST pin can be somewhat higher than 2VIN. The BOOST pin voltage should not exceed its absolute maximum rating of 40V. Figures 8(c) and (d) show how to bootstrap the SC2440 from a second independent power supply VS with voltage > 2.5V. DBST in Figure 8(d) prevents start up difficulty if VIN comes up before VS. Since the inductor current charges CBST, the bootstrap circuit requires some minimum load current to get going. Figures 9(a) and 9(b) show the dependence of the minimum input voltage required to properly bootstrap a 5V and a 3.3V converters on the load current. Once started the bootstrap circuit is able to sustain itself down to zero load. Shutdown and Soft-Start Each regulating channel of the SC2440 has its own softstart circuit. Pulling its soft-start pin below 0.8V with an open-collector NPN or an open-drain NMOS transistor turns off the corresponding regulator. The other regulator continues to operate. With one channel turned off, the internal bias circuit is kept alive. In the "Typical Characteristics", the soft-start pin current is plotted against the soft-start voltage with VIN = 5V. When one of
Since VOUT < VIN, DBST should always be tied to VOUT (if >2.5V) to maximize efficiency. Measurement of the 2channel regulator in Figure 1 shows that the efficiency penalties are about 1.3% (VOUT = 5V) and 2.2% (VOUT = 3.3V) with input bootstrapping. In general efficiency penalty increases as D decreases. Figure 8 summarizes various ways of bootstrapping the SC2440. A fast switching PN diode (such as 1N4148 or 1N914) and a small (0.1F - 0.47F) ceramic capacitor can be used. In Figure 8(a) the power switch is bootstrapped from the output. This is the most efficient configuration and it also results in the least voltage stress at the BOOST pin. The maximum BOOST pin voltage is about V IN + VOUT . If the output is below 2.8V, then DBST T will preferably be a small Schottky diode (such as BAT54) to maximize bootstrap voltage. A 0.33-0.47F bootstrap capacitor may be needed to reduce droop. Bench measurement shows that using Schottky bootstrapping diode has no noticeable efficiency benefit. The SC2440 can also be bootstrapped from the input (Figure 8(b)). This configuration is not as efficient as Figure 8(a). However this may be only option if the output voltage is less than 2.5V and there is no other supply with voltage higher than 2.5V. Voltage stress at the
Minimum Starting and Sustaining VIN vs Load Current
7.5 Minimum Input Voltage (V)
DBST TIED TO OUTPUT V OUT = 5V
Minimum Starting and Sustaining VIN vs Load Current
5.5 Minimum Input Voltage (V)
DBST TIED TO OUTPUT V OUT = 3.3V MA729
7.0 6.5
MA729
5.0
STARTING
STARTING
6.0 5.5 5.0 4.5 1 10 100 1000 Load Current (mA)
DBST TIED TO INPUT SUSTAINING
4.5
DBST TIED TO INPUT
4.0
SUSTAINING
3.5 0.1 1.0 10.0 100.0 1000.0 Load Current (mA)
(a)
(b)
Figure 9. Minimum Input Voltage Required to Start and to Maintain Bootstrap.(TA = 25C).
(c) 2005 Semtech Corp. 15 www.semtech.com
SC2440
POWER MANAGEMENT Applications Information
the soft-start pins is pulled low, 105A flows out of that pin. Pulling both soft-start pins below 0.2V shuts off the internal bias circuit of the SC2440. The total VIN current decreases to 38A. In shutdown either SS pin sources only 2A. A fast charging circuit (enabled by the internal bias circuit), which charges the soft-start capacitor below 1V, causes the difference in the soft-start pin currents. If either SS pin is released in shutdown, the internal current source pulls up on the SS pin. When this SS voltage reaches 0.3V, the SC2440 turns on and the VIN quiescent current increases to 3.3mA. The current flowing out of the other SS pin (which is still pulled low) increases to 105A. The fast charging circuit quickly pulls the released soft-start capacitor to 1V (slightly below the switching threshold). The fast charging circuit is then
2.4V 2V VSS 1V 0.3V 0 1V 0.74V Switc hing Starts 0
disabled. A 1.8A current source continues to charge the soft-start capacitor (Figure 3). The soft-start voltage ramp at the SS pin clamps the error amplifier output (Figure 2). During regulator start-up, COMP voltage follows the SS voltage. The converter starts to switch when its COMP voltage exceeds 1.1V. The peak inductor current gradually increases until the converter output comes into regulation. Proper soft-start prevents output overshoot during start-up. Current drawn from the input supply is also well controlled. Notice that the inductor current, not the converter output voltage, is ramped during soft-start. Both soft-start capacitors are charged to a final voltage of about 2.4V.
Hiccup Enabled
Fast Charge
VFB
Output must be at least 74% of its set voltage in this interval or the regulator will undergo shutdown and restart (hiccup).
Figure 10(a). Normal Soft-start.
2V VSS VCOMP 1V 0.3V 0
Switc hing
Not Switchi ng
Switc hing
Not Switchi ng
1V 0.74V VFB 0
Figure 10(b). Start-up Fails due to (i) Short Soft-start Duration or (ii) Output Overload or (iii) Output Short-circuited.
(c) 2005 Semtech Corp. 16 www.semtech.com
SC2440
POWER MANAGEMENT Applications Information
Overload / Short-Circuit Protection Each current limit comparator in the SC2440 limits the peak inductor current to 2.6A. The regulator output voltage will fall if the load is increased above the current limit. If overload is detected (the output voltage falls below 74% of the set voltage), then the regulator will be shut off. An internal 0.8A current sink starts to discharge the soft-start capacitor. As the soft-start capacitor is discharged below 1V, the discharge current source turns off and the soft-start capacitor is recharged with a 1.8A current source. The regulator undergoes soft-start. During soft-start (1V < VSS < 2V), the overload shutdown latch in Figure 3 cannot be set. When VSS exceeds 2V, the set input of the overload latch is no longer blanked. If VFB is still below 0.74V, then the regulator will undergo shutdown and restart. The softstart process should allow the output voltage to reach 74% of its final value before CSS is charged above 2V. Figures 10(a) and 10(b) show the timing diagrams of successful and failed start-up waveforms respectively. The soft-start interval should also be made sufficiently long so that the output voltage rises monotonically and it does not overshoot its final voltage by more than 5%. When starting into a shorted output, the SC2440 will repeatedly start and shut off ("hiccup"). VSS and VCOMP will appear as asymmetrical triangular waves [Figure 10(b)]. Power Good Indicators The PGOOD pins (Pins 11 and 14) are the open-collector outputs of the power good comparators. These slow comparators are incorporated with small amount of hysteresis. The FB low-to-high trip voltage of the power good comparators is 90% of the final regulation voltage. A pull-up resistor from each PGOOD pin to the input supply or the regulator output set the logic high level of the comparator. The power good comparator output becomes valid provided that VIN is above 0.9V. In shutdown the power good output is actively pulled low. A power good pull-up resistor tied to the input will therefore increase current drain during shutdown. Tying the power good pull-up resistor to the regulator output is preferred, as this will minimize the shutdown supply current. In shutdown there
SS1
PGOOD1 SS1
CONTROL1
CSS1
SC2440
OFF ON
CSS1
SC2440
PGOOD1
SS2
PGOOD2
SS2
PGOOD2
CONTROL2
CSS2
CSS2
CONTROL1 CONTROL2
OFF OFF
ON ON TD (a) (b)
Figure 11. Sequencing the Outputs by (a) Delaying Release of one Channel Relative to the Other and (b) Using the PGOOD of one Channel to Control the Other.
(c) 2005 Semtech Corp. 17 www.semtech.com
SC2440
POWER MANAGEMENT Applications Information
is no voltage at the switching regulator output or current in the PGOOD pull-up resistor. If the PGOOD output high level (= VOUT) is unacceptably low, then power good pullup from the input or a separate power supply will be the only choice. Sequencing the Outputs As mentioned above, pulling either soft-start pin low with an external transistor shuts off the corresponding regulator (Figure 11). Releasing the soft-start pin enables that channel and allows it to start. Delaying the release of the soft-start pin of one channel with respect to the other is a straightforward way of sequencing the outputs. Figure 11(a) shows this method using two external transistors M1 and M2. M1 is turned off first, allowing channel 1 to start. Channel 2 is then enabled after time T D. The PGOOD output of one channel can also be used in conjunction with the soft-start pin of the other channel to delay start of that regulator. This method is depicted in Figure 11(b). SS2 is pulled low and channel 2 is kept off until channel 1 output rises to 90% of its set voltage. A drawback of this approach is that only PGOOD2 is available as a logic output. Loop Compensation Figure 12 shows a simplified equivalent circuit of a stepdown converter. The power stage, which consists of the current-mode PWM comparator, the power switch, the freewheeling diode and the inductor, feeds the output network. The power stage can be modeled as a voltagecontrolled current source, producing an output current proportional to its controlling input V COMP . Its transconductance GMP is 5.7-1. With the current loop closed, the control-to-output transfer function v OUT has v COMP
a dominant-pole p2 located at a frequency slightly higher than that of the output filter pole. p 2 - nIOUT n =- VOUT C1 ROUT C1 (8)
where C1 is the output capacitor, ROUT is the equivalent load resistance and n (depending on duty ratio, slope compensation, frequency and passive components) is usually between 1 and 2. If C1 is ceramic, then its ESR zero can be neglected as it situates well beyond half the switching frequency. The low frequency gain of the control-to-output transfer function is simply the product of power stage transconductance and the equivalent load resistance (Figure 13). The transfer functions of the feedback network and the error amplifier are:
V
IN
POWER STAGE -1 GMP = 5.7 C11 GMA = -1 280 + RO C5 FB R1
I OUT VOUT ESR C1 ROUT
V COMP R5 C6
1V VOLTAGE REFERENCE
R2
Figure 12. Simplified Control Loop Equivalent Circuit
(c) 2005 Semtech Corp. 18 www.semtech.com
SC2440
POWER MANAGEMENT Applications Information
vFB R2 1 + sC11R1 = v OUT R1 + R2 1 + s R1R2 C11
(
)
(9)
forms a high frequency pole p 3 with R 5. Using the component values shown in Figure 1 for the 12V to 3.3V regulator (1.3MHz), RO = Amplifier Open Loop Gain 53dB = = 1.6M Transconduc tan ce 280 -1 1 1 =- ROC 5 1.6M * 470pF
1 1 =- R5 C 6 15.4K * 10pF
and
v COMP GMARO (1 + sC 5R5 ) vFB (1 + sC 5RO ) (1 + sC6R5 )
(10)
p1 = -
provided that C 5 >> C 6 and RO >> R5 . In Equation (10), C5 forms a low frequency pole p1 with the output resistance RO of the error amplifier and C6
Gain
= -1.3Krads-1 = -210Hz
p 3 = -
= -6.5 Mrads -1 = -1.0 MHz
T ( j)
R2 GMA RO R + R 1 2

R2 GMA R5 R1 + R 2 GMP R OUT 1 RO C 5
p1
v COMP v OUT
C C 1 R OUT n 1 R5 C 5 n R OUT C 1
p 2
Control-to-Output Transfer Function
1 R5 C 6 C
p 3
Z1
S 2
Figure 13. Bode Plots of Control-to-Ouput, Output-to-Control and the Overall Loop Gain. Control-to-output transfer function is shown with two poles near half the switching frequency S.
(c) 2005 Semtech Corp. 19 www.semtech.com
SC2440
POWER MANAGEMENT Applications Information
In addition C5 and R5 form a zero with angular frequency: Z1 = - 1 1 =- 15.4 K 470pF R5 C 5 the crossover frequency. However it reduces the phase margin. An estimate of R5 and C5 can be obtained from (11) and (12) with n=1. The compensation is then checked by measuring the loop gain and the phase or by observing the inductor current and the output voltage during load transient. Choose the largest R5 and the smallest C5 to give at least 45 of phase margin. The corresponding load transient should not show any ringing or excessive overshoot (see Figures 14(c), 14(d), 17(b) and 17(c)). C6 is a small ceramic capacitor (10-47pF) to roll off the loop gain at high frequency. Feedforward capacitor C11 boosts phase margin over a limited frequency range and is sometimes used to improve loop response. C11 will be more effective if R1 >> R1R2 . Example: Determine the compensation components for the 1.3MHz 12V to 5V and 3.3V converter in Figure 1. For both channels, S = 8.2 Mrads -1 , IOUT(MAX ) = 2A and C1 = 10F . n is assumed to be 1 in (11) and (12). For the 3.3V output: 23.3K 8.2 x 106 10 -5 R5 = 1 + 10K 10 (1) (5.7) (2.8 x 10 - 4 ) = 16.9K C5 = 10 -5 3.3 V = 1nF (1) 16.9 K (2A)
= -140 Krads -1 = -22 KHz The output-to-control transfer function
v COMP v COMP vFB = is also shown in Figure 13. Its midv OUT vFB v OUT R2 band gain (between z1 and p3) is GMAR5 R + R . The 2 1 overall loop gain T(s) is the product of the control-tooutput and the output-to-control transfer functions. To simplify T( j) Bode plot, the feedback network is assumed to be resistive. If the overall loop gain is to cross 0dB at one tenth of the switching frequency ( C = S f = ) at -20dB/decade, then its mid-band gain 10 5
(between z1 and p2) will be c = p 2 S 10 = SC1ROUT n 10n . C1ROUT
R2 This is also equal to GMPROUT GMAR5 R + R . Therefore 2 1 R2 C1ROUT GMPROUT GMAR5 R + R = 10n . 2 1
For the 5V channel: 40.2K 8.2 x 106 10 -5 R7 = 1 + 10K 10 (1) (5.7) (2.8 x 10 - 4 ) = 25.5K
Re-arranging, R SC1 R5 = 1 + 1 10nG G R2 MP MA (11)
C8 =
10 -5 5 V = 1nF (1) 25.5 K (2A)
z1 is shown to be less than p2 in Figure 13. Making z1 = p 2 gives a first-order estimate of C5: C5 = C1ROUT (MIN) nR5 (12)
Notice that R5 determines the mid-band loop gain of the converter. Increasing R 5 increases the mid-band gain and
(c) 2005 Semtech Corp. 20
C6 and C9 (both 10pF) are then added to increase gain margin. Load transient responses of both channels are observed using these values. There is very little inductor current overshoot even with C5 and C8 reduced to 470pF and 220pF respectively (Figure 14). The measured overall loop gain and phase plots of the converter are also shown.
www.semtech.com
SC2440
POWER MANAGEMENT Applications Information
Board Layout Considerations In a step-down switching regulator, the input bypass capacitor, the main power switch and the freewheeling diode carry switched currents with high di (Figure 15). dt
For jitter-free operation, the size of the loop formed by these components should be minimized. Since the power switches are already integrated within the SC2440, connecting the anodes of both freewheeling diodes close to the negative terminal of the input bypass capacitor minimizes size of the switched current loop. The input bypass capacitors should also be placed close to the
VIN=12V, VOUT=3.3V at 1.7A, C5=470pF, R5=15.4K and C6=10pF
VIN=12V, VOUT=5V at 1.7A, C7=220pF, R8=24.3K and C9=10pF
(a)
VOUT=3.3V
(b)
VOUT=5V
40s/div Upper Trace : OUT1 Voltage, AC Coupled, 0.5V/div Lower Trace : L1 Inductor Current, 0.5A/div (c)
40s/div Upper Trace : OUT2 Voltage, AC Coupled, 0.5V/div Lower Trace : L2 Inductor Current, 0.5A/div (d)
Figure 14. Overall Loop Gain and Phase versus Frequency for (a) Channel 1 and (b) Channel 2 of the Dual DC-DC Converter in Figure 1. (c) Channel 1 Load Transient Response, IOUT1 is switched between 0.3A and 1.7A. (d) Channel 2 Load Transient Response, IOUT2 is switched between 0.45A and 1.7A.
(c) 2005 Semtech Corp. 21 www.semtech.com
SC2440
POWER MANAGEMENT Applications Information
input pins. Shortening the traces of the SW and BOOST nodes reduces the parasitic trace inductance at these nodes. This not only reduces EMI but also decreases switching voltage spikes at these nodes.
V IN
VOUT
Figures 16(a) and 16(b) shows how various external components are placed around the SC2440. The frequency-setting resistor is placed next to the ROSC pin on the backside. The resistor is grounded to the ground plane, which is then tied to anodes of the freewheeling diodes with vias. These precautions reduce switching noise pickup at the ROSC pin. To ensure proper adhesion to the ground plane, avoid using vias directly under the device. In figure 15 two 12mil vias are placed at the edge of the underside pad.
ZL
Figure 15. Fast Switching Current Paths in a Buck Regulator. Minimize the size of this loop to reduce parasitic trace inductance.
VIN or VOUT1
GND
VIN or VOUT2
R5 R1 R2
C5
C8
R7
C6
R6
C7
C10
R8
C9
R4
R3
GND U1 R9 D3 C2 C4 GND VIN D1 L1 C15 D2 L2 D4
VOUT1
C1
GND
C3
VOUT2
(a)
(b)
Figure 16. Suggested PCB Layout for the SC2440. Notice that there is no via directly under the device and that the only component on the backside is the frequency-setting resistor. All vias are 12mil in diameter.
(c) 2005 Semtech Corp. 22 www.semtech.com
SC2440
POWER MANAGEMENT Typical Application Circuits
R6 100K FB1 PGOOD1 BOOST1 R5 15.4K C7 SS1 22nF R9 ROSC C10 22nF C9 COMP2 R7 22pF C8 13.4K 390pF FB2 GND BOOST2 R8 PGOOD2 100K SW2 C4 0.1F C3 20F R4 10K 15K SS2 D4 1N4148 SYNC C5 COMP1 390pF SW1 C2 0.1F D3 1N4148 L1 VIN 5V C15 IN 4.7F D2 UPS120 L2 1.8H R3 8.06K OUT2 1.8V/2A 1.4H D1 UPS120 C1 10F R1 23.2K R2 10K OUT1 3.3V/2A
Efficiency vs Load Current
95 90 85 Efficiency (%) 80 75 70 65 60 55 50 0 0.5 1 1.5 2 Load Current (A) V OUT2 = 1.8V VIN = 5V VOUT1 = 3.3V
SC2440
L1 & L2: Sumi da CR43
Figure 17(a). 1.3MHz 5V to 3.3V and 1.8V Step-down Converter
OUT1
OUT2
20s/div Upper Trace : OUT1 Voltage, AC Coupled, 0.2V/div Lower Trace : L1 Inductor Current, 0.5A/div (b)
20s/div Upper Trace : OUT2 Voltage, AC Coupled, 0.2V/div Lower Trace : L2 Inductor Current, 0.5A/div (c)
Figures 17(b) and 17(c). Load Transient Response. IOUT is switched between 0.3A and 1.75A.
(c) 2005 Semtech Corp.
23
www.semtech.com
SC2440
POWER MANAGEMENT Typical Application Circuits
R5
C5
FB1 COMP1 BOOST1 C2 0.1F SW1 SS1 VIN 5V
D3 BAT-54 L1 1.8H D1 UPS120 C15 C1 10F R1 30.1K R2 20K R11 4.02K OUT2 0.8V/2A OUT1 2.5V/2A R10 30.1K
14.7K C6 470pF C7 10pF 22nF
PGOOD1 SYNC R9 ROSC IN
4.7F
C10
12.1K SS2
SC2440
COMP2 SW2
D4 1N4148
D2 UPS120 L2 1H C4 0.1F
22nF C9 C8 R7 10pF 11.8K 470pF FB2 GND BOOST2 R8 PGOOD2 100K
C3 22F
R3 8.06K
L1 & L2: Sumi da CR43
Figure 18(a). Producing an Output Lower than FB Voltage. 1.5MHz 5V to 2.5V and 0.8V Step-down Converter R3 is a pre-load to shunt the current from R10 and R11 before PGOOD1 releases SS2.
Load Regulation
0.0
Percentage Deviation (%)
CH1
CH4
OUT1
-0.5
OUT2
-1.0
CH3
CH2
-1.5
2ms/div CH1 : OUT1 Voltage, 0.5V/div CH2 : OUT2 Voltage, 1V/div CH3 : SS2 Voltage, 1V/div CH4 : PGOOD2, 1V/div Figure 18(b). VIN Start-up Transient (IOUT1 = IOUT2 = 1A).
-2.0 0.0 0.5 1.0 1.5 2.0 Load Current (A)
(c) 2005 Semtech Corp.
24
www.semtech.com
SC2440
POWER MANAGEMENT Typical Application Circuits
R6 100K C5 C6 2.2nF COMP1 C7 10pF SS1 33nF SYNC R9 ROSC C10 33nF C9 COMP2 R7 10pF C8 11.8K 4.7nF FB2 GND BOOST2 R8 PGOOD2 100K SW2 C4 0.1F C3 10F X2 51.1K SS2 D4 1N4148 1F D2 UPS140 L2 6.8H R3 40.2K C13 68pF SW1 VIN 20V C15 47F C16 FB1 PGOOD1 BOOST1 C2 0.1F D3 1N4148 L1 D1 UPS140 15H C1 10F X2 R1 205K R2 51.1K C11 33pF C12 10pF OUT1 5V/2A
R5 22.1K
SC2440
IN
OUT2 1.8V/2A
R4 49.9K
C15 : 25V El ectrol ytic All Other Capacitor are C eramic.
L1 : Coiltronic DR74 L2 : Coiltronic DR73
Figure 19(a). 540KHz 20V to 5V and 1.8V Step-down Converter. Notice that Channel 2 is Bootstrapped from OUT1. This Bootstrapping Scheme Requires OUT1 to be Present at All Times (i.e. No Hiccup or Shutdown). Channel 2 will still Run if OUT1 is Absent. However its Power Disspation will be High.
VIN = 20V CH1 CH2
IOUT1 = 1A IOUT2 = 1A
1s/div CH1 : SW1 Voltage, 10V/div CH2 : SW2 Voltage, 10V/div
4ms/div Upper Trace : VIN, 10V/div Middle Trace : VOUT1, 2V/div Lower Trace : VOUT2 , 1V/div Figure 19(c). VIN Start Up Transient. IOUT1= IOUT2= 1.5A.
Figure 19(b). Switching Waveforms.
(c) 2005 Semtech Corp.
25
www.semtech.com
SC2440
POWER MANAGEMENT Outline Drawing - TSSOP-16 w/EDP
A e N 2X E/2 E1 PIN 1 INDICATOR ccc C 2X N/2 TIPS 123 e/2 B E D
DIM
A A1 A2 b c D E1 E e F L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.047 .002 .006 .031 .042 .012 .007 .003 .007 .193 .197 .201 .169 .173 .177 .252 BSC .026 BSC .112 .118 .122 .018 .024 .030 (.039) 16 0 8 .004 .004 .008 1.20 0.15 0.05 1.05 0.80 0.19 0.30 0.09 0.20 4.90 5.00 5.10 4.30 4.40 4.50 6.40 BSC 0.65 BSC 2.85 3.00 3.10 0.45 0.60 0.75 (1.0) 16 0 8 0.10 0.10 0.20
aaa C SEATING PLANE
D A2 A
C bxN bbb
A1 C A-B D H GAGE PLANE 0.25 (L1) L c
SIDE VIEW
SEE DETAIL F
A
01
EXPOSED PAD
DETAIL F
A
BOTTOM VIEW
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AB.
Land Pattern - TSSOP-16 w/EDP
X F
DIM
(C) F G Z C F G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.222) .126 .161 .026 .016 .061 .283 (5.65) 3.20 4.10 0.65 0.40 1.55 7.20
Y P
NOTES: 1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012-8790 Phone: (805)498-2111 FAX (805)498-3804
(c) 2005 Semtech Corp. 26 www.semtech.com

▲Up To Search▲

Price & Availability of SC2440TETRT

	To Download SC2440TETRT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .